A typical integrated circuit structure is made up of dies that include active devices such as transistors and capacitors. These devices are initially isolated from each other, and interconnect structures are later formed over the active devices to create functional circuits. On top of the interconnect structures, bond pads are formed and exposed on the surface of the respective die. Electrical connections are made through the bond pads to connect the die to a package substrate or another die. In certain categories of conventional packaging technologies, such as fan-out wafer level packaging (FO-WLP), a post-passivation interconnect (PPI) structure (also known as redistribution layers (RDLs)) may be formed over the passivation layers of a die and electrically connected to the bond pads. This is followed by the formation of a polymer layer and under bump metallurgies (UBMs). The UBMs are formed in openings penetrating through the second polymer and electrically connected to the PPI structure. I/O pads such as solder balls may then be placed on the UBMs. An advantageous feature of this packaging technology is the possibility of forming fan-out packages, which means the I/O pads on a die can be redistributed to a greater area than the die, and hence the number of I/O pads packed on the surfaces of the dies can be increased. However, an issue with this packaging technology is reliability concerns regarding delamination of the polymer layer. Delamination issues have been observed in typical FO-WLP wafers subject to various durability tests, such as a PCT-168 hrs test, wherein the wafer is stressed under a high heat, pressure, and humidity condition for 168 hours. These delamination issues may further cause I/O pad breakages in the integrated circuit.